The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
In general, a Schottky barrier is formed at the interface between a semiconductor and metal. Because of this, carrier conduction from the metal to the semiconductor is caused by the thermionic emission that carriers go beyond the Schottky barrier by thermal energy, or the tunnel effect that carriers tunnel through the Schottky barrier due to the quantum-mechanical effect, and the amount of the current is heavily dependent on the height and width of the Schottky barrier.
As an example of devices using such a Schottky barrier, a Schottky barrier metal insulator semiconductor (MIS) field-effect transistor (referred to as SB-MISFET hereinafter) has been proposed.
FIG. 13 is a cross-sectional view of a conventional SB-MISFET.
This SB-MISFET has, as shown in FIG. 13, a gate insulating film 103 formed on a silicon substrate 101, a gate electrode 104 formed on the gate insulating film 103, and a source region 110 and a drain region 111 which are made of metal or metallic silicide (for example, PtSi, CoSi2, or the like) and are formed to self-align with respect to the gate electrode 104.
In the SB-MISFET configured as above, since the source region 110 and the drain region 111 have been made of metal or metallic silicide, a Schottky barrier is formed between the source region 110 and the silicon substrate 101, and between the drain region 111 and the silicon substrate 101. When an ON-state voltage is applied to the gate electrode 104, band bending occurs in the silicon substrate 101, and the heights and widths of the Schottky barriers are effectively reduced. Because of this, carrier conduction from the source region 110 to the channel region is caused by the thermionic emission, tunnel effect, or the like, and the transistor operation is thus realized.
Furthermore, since the source region 110 and the drain region 111 have been made of metal or metallic silicide, they are able to have much lower resistances than a source region and a drain region which are formed by impurity doping into a semiconductor as used in an ordinary MIS field-effect transistor. Furthermore, since the depths of the Schottky junctions can be reduced quite easily by reducing the thickness of metal to be deposited, or by controlling the reaction between the metal and the silicon substrate, it is also expected to suppress the short channel effect. For this reason, it is expected that a high performance transistor will be provided by using an SB-MISFET in which the depths of the junctions and the parasitic resistance are reduced.
However, the heights and widths of the Schottky barriers are substantially determined by the difference between the electron affinity of the semiconductor and the work function of the metallic material, so that it is very difficult to control the carrier conduction from the metal to the semiconductor. For example, when silicon is used as the semiconductor, a metal-silicide is usually formed to obtain a good metal-semiconductor interface. And, when an ordinary large scale integrated circuit (LSI) is manufactured, metal used for the silicide is generally Ti, Co, Ni, or the like. Thus, there is a low degree of flexibility in selecting metallic material, and therefore the heights and widths of the Schottky barriers cannot be controlled freely.
Thus, in the SB-MISFET cited as an example of the background art, the height and width of the Schottky barrier between the source region and the channel region, on which the threshold voltage is dependent, are heavily dependent on metallic material used for the source region, so that the threshold voltage cannot be controlled freely. The source region and the drain region of the SB-MISFET are usually made using salicide (i.e., self-aligned silicide) process, and in order to prevent shorts between the gate region and the source/drain region, taking measures such as forming gate sidewall films (e.g., S1O2) having a sufficient thickness is required before the salicide process to increase the distance between the gate region and the source/drain region, a region between which is exposed for providing silicide.
At the same time, in order to suppress the short channel effect, the depth of the junction between the metallic silicide and the silicon substrate is required to be reduced by controlling the reaction between the metal and the silicon substrate. The amount of horizontal reaction of the silicide is as much as or less than the amount of in-depth reaction of it, so that an offset is easy to arise between the channel region and the source/drain region. If an offset arises, deterioration of the ON-state current caused by increase of the threshold voltage and/or increase of the parasitic resistance, decrease of the yield caused by increase of the threshold voltage variation, etc. become problems.
Furthermore, when an n-type device and a p-type device are fabricated on a substrate as in a complementary MIS (CMIS) field-effect transistor, etc., it is preferable that the source region and drain region of the n-type device are made of the same metallic material as one used for the source region and drain region of the p-type device in order to reduce the number of manufacturing processes. In this case, in order that the threshold voltage of the n-type device is as large as that of the p-type device, a metal used for the source region and drain region is selected from materials having a Fermi level near the middle of the forbidden band of the semiconductor. However, in this case, the heights of the Schottky barriers become as large as one-half of the energy gap of the semiconductor (about 1.1 eV in the case of silicon), so that it is difficult to obtain a sufficient large ON-state current.